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The IUP Journal of Telecommunications
Profiling Techniques in QuestaSim and Design of a Profiler Hardware Module
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Estimation of execution time for any module in software or in hardware guides the designer of its efficiency. The paper presents the profiling techniques present in QuestaSim hardware simulator for Field-Programmable Gate Array (FPGA) and System on Chips (SOCs). Different statistical and memory profiling techniques present in QuestaSim have been explained. An 8-bit Reduced Instruction Set Computing (RISC) processor has been designed for identifying the usefulness of the simulator. Various profiling reports have been generated and analyzed for the designed processor. The processor has been further extended by writing a module which counts the number of cycles taken by a unit. This module returns the count the number of times a function has been called. This module also gives the information such as how many different functions have been called, total number of different instructions, how many times each and function has been called.

 
 

The advent of embedded design flow in Field-Programmable Gate Array (FPGA) permits the creation of hybrid systems within a single FPGA fabric comprising software running on a processor, and custom digital hardware for accelerating computations and improving energy-efficiency (Cong and Zou, 2009; and Luu et al., 2009). It is estimated that over 40% of today’s FPGA designs contain embedded processors (Aggarwal and Marx, 2008). There is a need, then, for techniques that can profile the dynamic behavior of a program as it executes on an FPGA soft processor with the profiling results used for two key purposes: (1) improving the performance of the program itself, and (2) in the context of hardware/software codesign to aid in partitioning a program’s computations into those suitable for software versus hardware.

 
 

Telecommunications Journal, Profiling, QuestaSim, Profiling techniques, RISC processor, Hardware profiler