The use of electronic devices is increasing day-by-day in the form of static and dynamic devices, and simultaneously the energy consumption of these devices is increasing due to the rise in requirement of information processed (Datta et al., 2013). There is also the social need to reduce the power consumption of these devices. In the past four decades, efforts towards minimizing the transistor size for novel and small products have introduced some challenges in designing the small size (David and Massimo, 2014). As per the technology roadmap for semiconductors, the reduction in power consumption of the Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) used in today’s electronic circuits is now approaching the fundamental limit, and these days new types of device structures are being investigated as possible replacements for traditional MOSFETs.

The bipolar technology (bipolar junction transistor) has been replaced by the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) to reduce the power consumption and device size. MOSFET technology has proved to be a big success for the electronic industry in the last 40 years, and it helps a lot in terms of reduced area, low power, greater speed and low cost per chip. Moreover, different applications of these electronic devices demand ultra-low power consumption and prolonged battery lifetime, for example, radio frequency identification devices, portable electronics, implantable biomedical devices and microsensors. With the improvements in packaging and chip area (number of transistors per unit area), the problems related to power dissipation, cooling techniques, leakage current, heat removal and reliability have become a tradeoff, and therefore the requirement for energy-constrained design has increased. A number of power reduction techniques have been adopted by researchers such as supply voltage scaling, computer-aided design techniques for device sizing and interconnect, switching activity reduction, logic optimization, architectural techniques of pipelining and parallelism. Out of these techniques, the most prominent approach, which significantly reduces both active and static components of power, is scaling the supply voltage.

Minimum energy per operation can be achieved by operating the transistor in the subthreshold region (NIAIST, 2013). A transistor operating in subthreshold region is good for ultra low power requirement application like RFID, wireless microsensors and biomedical implants.
The following are the probable reasons behind these optimization requirements. If we do not adopt low power design, then battery size will increase up to 30% to 40% over the next five years.

Telecommunications Journal,Metal Oxide Semiconductor Field Effect Transistor (MOSFET), TFET, FinFET, HTFET, SE-HTFET, SOI, Short Channel Effects (SCE)