An energy-efficient single bit full adder based on energy recovery CMOS XOR/XNOR using Clocked Adiabatic Logic (CAL), 2N-2N2P and transmission gate multiplexer has been presented in 0.35 µm technology. The adder using CAL (20T) XNOR/XOR and multiplexer-based architecture gives a power dissipation of 661.2466 µW, whereas the architecture based on CAL (18T) dissipates 661.315 µW. Further, the adder designed with 2N-2N2P (16T) XNOR/XOR and multiplexer approach dissipates minimum power of 642.4407 µW. Moreover, the effect of gate length of transistor has also been considered for the evaluation of power dissipation. By varying the gate length of the transistor from 0.35 µm to 1 µm, an improvement of 63.25%, 67.91% and 2.56% in power consumption has been achieved using CAL (20T) XNOR/XOR, CAL (18T) XNOR/XOR and 2N-2N2P (16T) respectively.

Adders are the basic element of many VLSI systems and are used in various arithmetic operations like subtraction, multiplication and division. So designing a single bit full adder cell is a significant step for building large VLSI systems. Reducing the power consumption and delay in adders is the major goal to be achieved in most VLSI systems. The exclusive-OR (XOR) and exclusive-NOR (XNOR) gates are the basic building blocks of large circuits like full adder and parity checkers. Hence, optimized designs of these gates enhance the performance of circuits like full adders, as these gates are used as sub-blocks in large circuits. Power consumption in adders also affects the power bill of a VLSI chip and increases with the increase in the number of components on the chip. With the increase in the operating frequency of the system, power consumption increases at a rapid rate. The need for ultra-fast systems with high frequency further aggravates the problem of power dissipation. The designers now focus not only on the performance of these systems but also on the power consumption of VLSI circuits. The problem of power consumption has to be addressed by the researchers without compromising the speed of these systems.

The conventional approaches for power reduction seek to reduce the power supply voltage, decrease the load capacitance or reduce the number of transitions on the node. But to achieve a significant noise margin, a suitable level of supply voltage is mandatory. Power consumption is also reduced with reduction in power supply voltage but at the cost of current leakage (Chandrakasan et al., 1992; and Chandrakasan and Brodersen, 1995). A number of techniques have been proposed for the single bit full adder design, including the Complementary Metal-Oxide Semiconductor (CMOS) adder, Static Energy Recovery Full adder (SERF), Transmission Function Adder (TFA), Complementary Pass Transistor (CPL) adder, etc. (Ahmed and Magdy, 1997 and 2000; Al-Sheraidah et al., 2001; Hung et al., 2002; Jyh-Ming et al., 2004; Yingtao et al., 2004; Jin-Fa et al., 2007; and Moradi et al., 2009).

Electrical and Electronics Engineering Journal, Energy-Efficient Full Adder Design, Energy Recovery Gates, Multiplexer Architecture, VLSI Systems, Power Consumption, Static Energy Recovery Full Adder, SERF, Complementary Metal-Oxide Semiconductor, CMOS, PMOS Transistors, Energy Recovery Techniques, Transmission Gate Multiplexer.