New Digitally Controlled Oscillator (DCO) structures based on delay cells with novel three-transistor NAND gate are presented in this paper. Two design approaches for new delay cell are presented. Three, five and seven-stage DCO is implemented with the first approach. Further, a four-bit controlled DCO is implemented with the second approach. The output frequencies are controlled digitally with digital bits of different lengths applied to delay cells. Three-bit control DCO shows the output frequency variation in the range of 3.7471-3.9806 GHz and power consumption varies 0.5411-1.2336 mW with control word 111-000. Five-bit controlled DCO shows the frequency and power variation of 2.1727-2.3097 GHz and 0.9019- 2.0560 mW respectively, with varying control word 11111-00000. Moreover, seven-bit controlled DCO shows the frequency and power consumption variation of 1.5615-1.6622 GHz and 1.2721-2.7767 mW respectively, with varying control word 1111111-0000000. Further, a four-bit controlled DCO with delay cell using the second approach shows the frequency and power variation of 1.6799-2.0172 GHz and 1.2276-3.9973 mW respectively, with control word 1111-0000. The first approach gives better results in terms of power dissipated, whereas the second gives wider range of output frequency. Further, the power consumption and output frequency of proposed circuits are compared with earlier reported circuits, and the present approach shows significant improvements.

Phase Locked Loops (PLL) are the commonly used circuit component in modern communication systems with wide application in frequency synthesis, clock and data recovery (Dunning et al., 1995; Boerstler, 1999; and Hsu et al., 2001). Analog PLL have disadvantage of sensitivity towards process variation and high power consumption. With the advent of Very Large Scale Integration (VLSI) technology, All Digital Phase Lock Loops (ADPLL) have become essential building blocks in digital circuits (Dunning et al., 1995; Chiang and Chen, 1998; Jen-Shiun and Kuang-Yuan, 1999; and Jun and Young-Bin, 2010). Digital controlled PLL are more robust, consume less power and require less area on chip. Oscillators are the central components of any PLL system and Digital Controlled Oscillators (DCO) are the replacement of Voltage Controlled Oscillator (VCO) in ADPLL. There are two parameters which modulate the output frequency of ring oscillator: one is propagation delay of each delay cell, and other is total number of delay cell in closed loop (Jun and Yong-Bin, 2008). Digital controlled delay cell being the fundamental component of DCO, its optimized design can give superior performance. There are three major techniques for varying the delay of delay cell. The first technique is driving strength fixed capacitive loading (Martin and Gabriel, 2001; and Staszewski and Balsara, 2005), while the second technique uses shunt capacitor technique to tune the capacitive loading (Raha et al., 2002; Mohammad and Manoj, 2003; Staszewski et al., 2003; and Pao-Lung et al., 2005). A conventional shunt capacitance digital control delay cell is shown in Figure 1. Adding more capacitances increases the operating range, but power consumption also increase at the same time. The third technique is based on variable resistor of digitally controlled cells (Saint-Laurent and Swaminathan, 2001). Power consumption is becoming an important design criteria nowadays for any VLSI system design (Kaushik and Sharat, 2002). Widespread use of battery-operated mobile device has further added to the research efforts for power saving. DCO being the major component of PLL system, is also responsible for most of the power consumption.

Telecommunications Journal, Digital Control Oscillator (DCO), Delay cell, Power consumption, Variable capacitance,
Voltage Controlled Oscillators (VCO).