With continuous technology scaling, minimizing leakage power has become the prime area of concern in digital circuits. Different techniques were proposed to minimize the active leakage power in sub-micron technologies. In this paper, reduction in leakage power of 6T Static Random Access Memory (SRAM) is proposed using power gating technique. Power gating is the most effective technique to reduce the sub-threshold leakage current in the digital circuits. Initially, different analyses were done in terms of voltage scaling and sleep transistor width considering the Static Noise Margin (SNM), delay and power consumption in 6T SRAM. The analysis of power consumption was carried out with or without power gating using extensive simulation over HSPICE. The simulation results are based on the 32 nm and 45 nm Berkeley Predictive Technology Model (BPTM). The simulation results showed the effective leakage reduction and delay improvement with cell stability in memory array operation compared with the conventional 6T SRAM.

With increasing clock frequency and need for large quantity of data at very high speed, continuous efforts were made to design a low power and high performance Static Random Access Memory (SRAM) designs. SRAM is the critical component of the handheld devices and high speed processors and serves as the building block of System on Chips (Socs). Due to continuous technology scaling, power consumption has become a major area of concern in CMOS designs to achieve high integration density with reliability and cell stability. The main contributor of power consumption in a circuit is leakage power. Since the memory spends almost its entire operating time in the idle mode, it is difficult to reduce the leakage power consumption while maintaining good stability with less degradation of Static Noise Margin (SNM).

In this paper, power gating technique is applied to 6T SRAM to achieve good stability and less leakage power consumption in the circuit. Power gating is an effective technique to provide high performance in the active mode and save maximum leakage power dissipation during the standby mode. In this technique, energy dissipation is reduced by cutting off the power supply to the parts of the circuits whenever the circuit is in sleep mode. Power gating uses low leakage PMOS and NMOS transistor as header and footer switches, respectively, that cut off the logic block from the power supply and ground during idle mode operation. The sleep transistors used in the power gating are basically high threshold transistors and mostly considered as Multi Threshold CMOS (MTCMOS). Power gating is the most commonly used technique that provides leakage power reduction, high performance and state retention in the circuits.

Electrical and Electronics Engineering Journal, 6T SRAM, Low power, CMOS circuits, Power gating, SNM, Simulation