The paper describes the design and analysis of CMOS Voltage Controlled Ring Oscillator (VCRO) based on the delay cells proposed by Changzhi and Jenshan (2010). The two-stage CMOS VCRO exhibits very low power consumption and wide tuning range when realized using GPDK 45 nm CMOS process. The design parameters of the transistors in the delay cell are chosen at a minimum scale in this technology so as to achieve the lowest power consumption. The oscillator has a very low power consumption of 2.97 mW with a supply voltage of 1 V. This also exhibits a wide tuning range from 6.4 GHz to 16.4 GHz. Because of its wide tuning range, it can be used for electronic warfare applications. The phase noise of this ring oscillator is found to be –78 dBC/Hz @10 MHz offset which can be improved by increasing the size of the transistors and adding more number of stages. The layout of the VCRO is created using the Cadence virtuoso layout XL tool, which shows that the chip area is 2.82 × 3. 67 mm.

Phase Locked Loop (PLL) is used in a wide range of communication systems for synchronization and demodulation process. Voltage Controlled Ring Oscillator (VCRO) is one of the key components in a PLL. The wide frequency range of PLL attributes to the tuning range of VCO. Hence VCO with a wider and linear tuning range is extensively used in various applications such as radar, electronic warfare and electromagnetic weapons like electromagnetic generators. The design of a high performance CMOS VCO in terms of optimized parameters like tuning range, power consumption and phase noise has been a challenging task in recent years. A CMOS VCO can be implemented using LC tuned circuit or ring topology. LC-oscillators proposed by Craninckx and Steyaert (1997) and Bozorg and Mohammad (2014) exhibit good phase noise performance, but it fails in other aspects like, firstly, the operating frequency is low as compared to ring oscillators. Secondly, the chip area is very high due to the presence of spiral inductors which leads to high cost. Thirdly, the phase noise performance factor depends on the quality factor of inductors as a result of which the cost of a good quality LC oscillator is high (Razavi, 1996; and Baker and Boyce, 2002). On the contrary, ring oscillators provide much better tuning range and occupy very less chip area for fabrication which is very cost-effective. It can generate both in-phase and quadrature outputs for even number of delay cells.

Telecommunications Journal, CMOS, VCRO, Low power, Phase noise, Ring oscillator, Electronic warfare