| Pub. Date | : May, 2019 |
|---|---|
| Product Name | : The IUP Journal of Telecommunications |
| Product Type | : Article |
| Product Code | : IJTC41905 |
| Author Name | : Veski Dabas and Surender Kumar Grewal |
| Availability | : YES |
| Subject/Domain | : Science & Technology |
| Download Format | : PDF Format |
| No. of Pages | : 14 |
In this paper, a new design of 6T XOR circuits based on Carbon Nanotube Field Effect Transistor (CNTFET) technology in 32 nm technology length is proposed for evaluation. They are simulated using HSPICE, and the performance parameters such as average power, power dissipation voltage source, PDP and delay are determined. The proposed circuit is compared with 12T CMOS XOR circuit which is conventionally used and compared with CNTFET counterpart of the XOR gate. The simulation results showed that the proposed 6T XOR gate is better in performance.
In a MOSFET, the source and deplete areas are associated with a leading surface channel through which bearers can stream when legitimately regulated by the door voltage (Radha and Rahul, 2014). The source and deplete areas can be either p- or n-type, yet they both should be of a similar sort, and of an inverse kind to the body district. Of late, MOSFETs have been downsized fundamentally and the Si-SiO2 interface remains the most critical mix (Ronak et al., 2014). Downsizing the measurements of MOSFETs is a constant pattern. The challenges with diminishing the extent of the MOSFET incorporate the semiconductor gadget manufacture process, the requirement for low voltages, and with poor electrical execution, the need for circuit upgrade and advancement (Pramod and Dinesh, 2015). It has been expressed that little transistors switch quicker, which is the primary inspiration for downsizing the measurements of semiconductor gadgets (Srikanth et al., 2015).
Carbon Nanotube Field Effect Transistor (CNTFET), Nanotubes, 6T XOR, 32 nm