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The IUP Journal of Telecommunications

Optimization of SRAM Cell Using 32 nm FinFET Technology

Article Details

Pub. Date	: May, 2019
Product Name	: The IUP Journal of Telecommunications
Product Type	: Article
Product Code	: IJTC51905
Author Name	: Mamta and Surender Kumar Grewal
Availability	: YES
Subject/Domain	: Science & Technology
Download Format	: PDF Format
No. of Pages	: 11

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Abstract

CMOS technology is the most feasible semiconductor technology, but it fails to perform as per expectations beyond and at 22 nm technology node due to short channel effects. Multigate Field Effect Transistor (FET) like FinFET is the most viable substitute for MOSFETs at 22 nm and beyond. In this paper, different configurations of Static RAM (SRAM) cells (6T, 8T and 10T) are designed and implemented using FINFET technology to improve their power and speed. A 2-bit and a 4-bit SRAM are also implemented using the optimized circuit (10T) of SRAM cell. Also, a comparative study is made for various performance parameters like average power and delay. It can be concluded that the FinFET technology can effectively reduce power. Due to limited amount of power consumption, it can be used in a number of electronic devices.

Description

Mass CMOS advancements have been the foundation of semiconductor gadgets for a considerable length of time. Moore’s law rouses the innovation scaling to enhance the execution highlights, for example, speed, control utilization and zone (Vivek et al., 2016; and Sudarshan and Kanchana, 2017). But with aggressive downscaling, significant challenges have also been seen, for example, Short Channel Effects (SCEs), i.e., as the miniaturization takes place, the bulk CMOS faces various challenges (Ajay and Niraj, 2013; and Kushwah et al., 2016). Scaling of MOS ends up being widely troublesome for innovation underneath 32 nm, where the proximity of source and drain cuts down the control of the entryway (Navneet et al., 2016; and Nidhi, 2016).