Over the past decade, steady advances in VLSI technology
and design tools have extensively expanded the application
domains. This is because of the increasing demands of silicon
reuse, product upgrade after shipment and bug-fixing ability.
Due to its potential to greatly accelerate a wide variety
of applications, Reconfigurable Computing Systems (RCS)
have emerged as a promising implementation platform to provide
flexibility, high-performance and low-power for future System-on-Chip
(SoC) designs. To specify the design and implementation
of such complex systems, incorporating the functionality
implemented in both hardware and software forms, we are
compelled to move on from traditional Hardware Description
Languages (HDLs). Since C and C++ are dominant languages
used by chip architects, system engineers and software engineers
today, we believe that a C++-based approach to hardware
modeling is necessary. This will enable codesign, providing
a more natural solution to partitioning functionality between
hardware and software. In this paper, we discuss a design
approach of System C (a C++ class library) for RCS at the
system-level which provides the necessary features for modeling
design hierarchy, concurrency and reactivity in hardware.
Traditionally, microprocessors are the soul of most high-performance
systems. They facilitate a flexible computing platform and
are able to perform a vast range of applications. Today,
customers are demanding products having characteristics
of high bandwidths, high quality, low power consumption
and low cost. General Purpose Micro Processors (GPPs) are
not capable of providing such optimal solutions to meet
these demands. For a GPP, the functionality of each component
is fixed, i.e., the applications are performed by interpreting
a sequence of instructions from software and functioning
on data stored in the memory hierarchy. Thus, the same fixed
hardware can be used for many general purpose applications.
Application Specific Integrated Circuits (ASICs) have provided
an alternate way to solve the performance issues of GPPs
[14]. These are designed for a particular class of applications
having common characteristics. Thus, it limits the flexibility
of the architecture and eliminates any post-design optimization
and upgrades in features and algorithms. Traditional Field
Programmable Gate Arrays (FPGAs) are also capable of providing
flexible design solutions, but they have limitations such
as long configuration and compilation time, coarse logic
element granularity and restricted reconfiguration bandwidth.
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