The paper presents the methodological algorithm of partial reconfiguration flow for execution and implementation of Reconfigurable Modules (RMs) on Xilinx Virtex-4(XC4VFX12) device. Its interface controller through UART for 32-bit RM was designed. An interactive interface was created for a system designed with static as well as dynamic parts. Using this interface, operands are assigned to the 32-Bit arithmetic and logical RMs at run-time. The dynamic part included the two reconfigurable regions which were allocated to execute various logical and 32-bit arithmetic modules in a time-shared manner. Static part was the region of the design that did not change during partial reconfiguration and contained the logic to control the partial reconfiguration process. To verify partial reconfiguration execution at run-time, an interface was designed to make user interaction with the system at run-time. Interface design included the controllers for controlling the flow of data to and from the reconfigurable modules to the external world (host environment) through bus macros. The controllers were designed as static modules. All the modules, static as well as dynamic were designed and simulated to verify the functionality with supporting simulation tool using ModelSim-6.0d and synthesized with Xilinx 9.1.02i_PR10 (ISE).

Reconfigurable computing is the new paradigm satisfying the contradictory requirements of flexibility and performance in the modern computing world. It allows the system hardware to be changed periodically in order to execute different applications on the same hardware. Partial reconfiguration allows time-sharing of physical resources for the execution of multiple functional modules by restructuring the hardware at run-time without incurring any system downtime. This results in dramatic increase in speed and functionality of FPGA-based system. Basically, there are two conventional ways to perform computation, hardware-based and software-based. Performance and flexibility are the two key parameters to choose a system for a specific application. The first method uses the hardware, such as application-specific integrated circuits (ASICs) and application-specific instruction set processors (ASIPs), and gives us much performance as hardware optimized for a particular application, but not flexibility. Also, it may not be cost-effective to modify or add more features, once the hardware is customized for a given application. Whereas, the second method is based on general purpose microprocessor (GPP) or microcontroller-based computing.

This paper focuses on: (1) A system design with two partial reconfiguration regions (PRRs), one (PRR1) consisting of two arithmetic functional modules (32-bit ADD/SUB) and the other (PRR2) consisting of left and right shifting functional modules for LEDs on board; (2) Implementation of system on XC4VFX12 FPGA device; and (3) User interface designed for interacting with the implemented system while swap modules in and out from the device during run-time. The paper is organized as follows: Section 2 describes the partial reconfigurable design methodologies. Section 3 describes the design of controller for interactive interface. Section 4 includes the hardware implementation results, placement and floorplan of the top-level design. Finally, Section 5 includes the conclusions drawn and future scope related to this work.

Science and Technology Journal, Methodological Algorithm, Partial Reconfiguration Flow, Physical Resources, Design Parameters, Global Signals, Initial Budgeting, State Machine Model, Boundary Scan Mode, Reconfigurable Computing Systems, Power Consumption, Intelligent Robotic Systems.