| Pub. Date | : Jan, 2021 |
|---|---|
| Product Name | : The IUP Journal of Electrical and Electronics Engineering |
| Product Type | : Article |
| Product Code | : IJEEE10121 |
| Author Name | : Gyanender Kumar, Sachin Kumar Yadav |
| Availability | : YES |
| Subject/Domain | : Engineering |
| Download Format | : PDF Format |
| No. of Pages | : 14 |
The requirement for maximum noise-tolerant SRAM cells with low dissipating power is increasing day-by-day. The paper presents 9T SRAM cell which targets certain stability parameters, capable of tolerating the maximum noise with low dissipating power. 9T SRAM is an isolated SRAM with two separate read ports that help in enhancing the stability parameters. This is done at 1 V using a 45 nm technology node. For simulation and analysis of stability parameters, Cadence Virtuoso and EDA tanner tools are used. The work is also compared with previous works of various 6T, 7T and 8T SRAM cells.
Enhanced transmission capacity and impressive execution are the advantages of System-on-Chip (SOC) which are made from huge embedded memories. However, implanted SRAMs are the most reliable installed recollections utilized in the present SOCs. SRAM's intractability with basic Complemetary Metal Oxide Semiconductor (CMOS) innovation gives a plentiful chance to turn the most elevated zone market of numerous SOCs going from an elite server processor to a HDTV video processor, as given in Figure 1. In contrast to DRAMs, SRAMs are very fast and do not require an information reviving instrument. As the innovation scales, the thickness of the transistors in the SRAM units increments significantly. As the innovation scales, the leaking current turns into a noteworthy concern. Agreeing to Robert (1997), the leaking current is one of the significant difficulties in basic CMOS SOCs.
6T SRAM cell, Power dissipation, Read delay, SNM, Write delay