Jan'21
The IUP Journal of Electrical and Electronics Engineering
Focus
In the Visible Light Communication (VLC) technology, data is transmitted at high speed by modulating the intensity of light from a light source. A photodiode device transforms the data into usable form. VLC can be used for the initial configuration of the IoT devices such as wireless sensors. In the paper, "A New Architectural Approach to VLC Application", by Suhas Deshpande, Ashwini Benni and S C Sajjan, a new architecture is proposed for implementation of VLC in outdoor application. When environmental factors like snow, fog, rain, dust, etc. are involved, an AI integrated VLC system is proposed to be used.
Arithmetic Logic Unit (ALU) in VLSI circuits consists of full adder circuits, in which power consumption is an important design aspect. In the paper, "4-Bit Ripple Carry Adder Using Area-Efficient Full Adder in CMOS Technology", by Gyanender Kumar and Lincoln Hadda, various full adder circuits are analyzed with respect to power consumption and speed.
Power quality issues like harmonic distortions in the grid connected solar photovoltaic system can be mitigated by proper control design. In the paper, "Enhanced PLL for Three-Phase Single-Stage Multifunctional Grid-Connected SPV System", by Hareesh Kumar Yada and M S R Murthy, design of a simple and robust controller with a three-phase dual Enhanced Phase Locked Loop (EPLL) is presented. The SPV fed inverter acts a DSTATCOM for mitigation of harmonics and reactive power compensation to improve line power factor even while transferring the real power into grid. The proposed controller is tested in MATLAB/Simulink environment with Simpower systems block set.
Consulting Editor
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| Article | Price (₹) | ||
| Design and Performance Analysis of SRAM Cells |
100
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| A New Architectural Approach to VLC Application |
100
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| 4-Bit Ripple Carry Adder Using Area-Efficient Full Adder in CMOS Technology |
100
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| Enhanced PLL for Three-Phase Single-Stage Multifunctional Grid-Connected SPV System |
100
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Design and Performance Analysis of SRAM Cells
The requirement for maximum noise-tolerant SRAM cells with low dissipating power is increasing day-by-day. The paper presents 9T SRAM cell which targets certain stability parameters, capable of tolerating the maximum noise with low dissipating power. 9T SRAM is an isolated SRAM with two separate read ports that help in enhancing the stability parameters. This is done at 1 V using a 45 nm technology node. For simulation and analysis of stability parameters, Cadence Virtuoso and EDA tanner tools are used. The work is also compared with previous works of various 6T, 7T and 8T SRAM cells.
A New Architectural Approach to VLC Application
During the last decade, the exponential growth of mobile devices and wireless services created an enormous demand for radio frequency-based technologies. Meanwhile, the industry has been revolutionized thanks to the popularization of Light Emitting Diode (LED) light bulbs, which are more economical and efficient. In this context, Visible Light Communication (VLC) may be a disruptive technology supported by LEDs that gives free spectrum and high rate, which may potentially function as a complementary technology to the current radio frequency standards. In the current scenario, there is a lot of increased usage of frequency (RF) for mobile communications. The paper reviews the VLC technology and replaces a small part of implementation of RF in communication usage.
4-Bit Ripple Carry Adder Using Area-Efficient Full Adder in CMOS Technology
Basic functions of arithmetic operation are addition done by Full Adder (FA) which plays a significant role in different areas, including Very Large-Scale Integrated Circuits (VLSI), Microprocessors (MP) and Digital Signal Processing (DSP). Hence, the proposed designs of 32T and 112T are a viable option for low power complex system design. The power consumption and speed for 28T 1-bit adder are 9.9 mW and 35 ps, respectively. The power consumption and speed for 8T 1-bit adder are 4.8 mW and 20 ps, respectively. The speeds for 112T 4-bit adder and 32T 4-bit adder are 160 ps and 89 ps, respectively.
Enhanced PLL for Three-Phase Single-Stage Multifunctional Grid-Connected SPV System
The paper presents a multifunctional inverter for a three-phase single-stage grid-connected Solar Photo-Voltaic System (SPV) system with Enhanced Phase Locked Loop (EPLL)-based control algorithm. The EPLL-based Quadrature Signal Generation (QSG) estimates the magnitude of source voltage and load current signal and Phase-Locked Loop (PLL) estimates phase angle of the grid voltage. This estimation is used to design a proper controlled algorithm which improves the power quality such as reactive power compensation, harmonic rejection and DC offset rejection, in addition to feeding the SPV energy to load and grid. Perturb and Observe (P&O)-based Maximum Power Point Tracking (MPPT) is used to estimate the reference PV voltage signal and power. The EPLL-based controller tracks the signal even under distorted grid supply conditions such as voltage sag/swell and harmonics to improve the dynamic response. These multifunctional capabilities of the inverter make the system more efficient for feeding the SPV energy to grid. Various operating conditions are shown to validate the proposed controlled algorithm using MATLAB/Simulink.