A universal asynchronous receiver and transmitter (UART) is an indispensable component for communication with serial input and output devices. Serial communication [1-3] is essential in computers and allows them to communicate with the low speed peripherals such as keyboard, mouse and modems. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART reassembles the bits into complete bytes [4, 5]. Figure 1 illustrates a basic UART data packet. It consists of 1 start bit which is always at logic 0, followed by a programmable number of data bits (typically between 5 to 8), and a programmable number of stop bits (1 or 2) [2]. The stop bit is always kept at logic 1. Thus, a standard UART can transmit 10 bits of data byte. In the UART, the two systems transmitter and the receiver do not share a clock signal and they contain separate local clocks [6].

Since common clock is not shared, a known data transfer rate (baud rate) must be agreed upon between the transmitter and the receiver before the transmission and reception of data bit. The transmitter shifts out the data starting with the least significant bit (LSB) first. Once the required baud rate is established (prior to initial communication), both the transmitter and the receiver's internal clocks are set to the same frequency (though not in the same phase). The receiver `synchronizes' its internal clock to that of the transmitter's at the beginning of every data packet received.

The paper is arranged as follows: after a brief introduction in Section 1, Verilog designing of UART has been discussed in Section 2. The results and discussion of simulation and synthesis are given in Section 3, followed by a conclusion in Section 4.

The proposed transmitter of UART is composed of a memory element, a baud rate circuit, a bit cell counter, transmitted bit counter, a shift register and a state machine. The memory element stores the data byte to be transmitted. The size of the memory element is 20 bytes by default. It can be varied according to the requirement. The baud rate circuit is used to provide the necessary baud clk to the transmitter. The baud rate circuit is explained in Section 2.3. The Xmit bit counter is used to keep track of the number of data bits cumulated so far. When this count reaches a preset limit (i.e., 8), the state machine stops accepting more data bits. This counter has 2 control inputs: enabitcountH and rstbitCountH. When the former is active high, the counter is advanced by 1. When the latter is active high, the counter is cleared to 0. The width of this counter is of 4-bits by default. The main function of bit cell counter is to generate a delay in units of uartclk (Baud rate Period/16). This is an up counter and the signal countEnableH1 controls it. When countEnableH1 becomes active high, the counter is in a reset state. When this signal is active low, the counter counts up by 1. Figure 2 illustrates the functional block diagram and Table 1 indicates the input and output ports of the transmitter.

Science and Technology Journal, Universal Asynchronous Receiver And Transmitter, UART, FPGA, Verilog Hardware Description Language, VHDL, Baud Rate Generator, Total Power Consumption, National Semiconductor Application, Applied Electromagnetic, Mobile Robots,UART System, Least Significant Bit.