Arbiters are electronic devices used in digital systems to order computational activities for shared resources. Asynchronous digital circuit designs claim to yield better results in the following areas of designers' interest: power efficiency, modularity, average-case performance, clock skew, adaptability to processing and environmental variations, concurrency, reusability, noise immunity and metastability. This paper presents the design and performance evaluation of a 4 ´ 1 asynchronous arbiter. In order to compare the performance of this asynchronous arbiter, a synchronous arbiter with similar specifications as that of asynchronous arbiter has been designed. The arbiters have been designed, coded and simulated using Verilog Hardware Description Language (HDL). The hex file has been generated using Xilinx tool and downloaded into the Field Programmable Gate Array (FPGA) kit. The measured performance parameters indicate that the asynchronous 4 ´ 1 arbiter consumes less power, offers higher throughput, higher frequency of operation and lower latency, compared to the synchronous 4 ´ 1 arbiter.

All forms of asynchronous circuits are concerned with providing hazard-free or glitch-free outputs. The motivation behind pursuing the asynchronous circuit, is to achieve low-power circuit operation. Low-power synchronous circuits usually involve shutting down the clock to subsystems, which are not needed at a particular time. Clocks must be continuously supplied to the subcomponent. Hence, power is consumed even during idle periods. Asynchronous circuits go into the idle mode for free since, there are no transitions in the idle mode. Moreover for an active system, only the subsystems that are required for the computation at hand, dissipate power. Asynchronous design has been an active area of research since the mid 1950s, but is yet to achieve widespread usage (Ebergen, 2004). Nowick and Dill (2000) have presented the complete analysis and synthesis of both synchronous and asynchronous sequential circuits. Hauck (1995) and Myers (2001) have examined the benefits and problems inherent in asynchronous computations in some of the more notable design methodologies.

Arbiters are digital circuits that resolve conflicts between two concurrently arriving signals to access common resources. They are required in computers which have multiple Central Processing Units (CPUs) or other devices accessing memory, and have more than one clock. It is possible for requests from two unsynchronized sources to come in, at nearly the same time. The arbiter must then decide which request to be serviced first. Plummer (1972) has discussed the design of asynchronous arbiters, and its complexity. Shin et al. (2002) have explained the round-robin arbitration scheme, and Chao et al. (1999) have proposed a ping-pong arbitration scheme.

Telecommunications Journal, Arbiter, Asynchronous Arbiter, Synchronous Arbiter, Digital Circuit, FPGA Component, Field Programmable Gate Array, FPGA, Hardware Description Language, HDL, Central Processing Unit, CPU, Static Random Access Memory, SRAM, Static Timing Analysis Tool, Global Telecommunications Conference, Field Programmable Gate Array, FPGA.