AM-FM Features and Their Application to Noise Robust Speech Recognition: A Review

-- Vibha Tiwari and Jyoti Singhai

The extraction and selection of the best parametric representation of acoustic signals is an important task in designing any speech recognition system. A wide range of possibilities exists for parametrically representing the speech signal for the speech recognition task such as Linear Prediction Coding (LPC), Mel Frequency Cepstrum Coefficients (MFCCs) and others. MFCCs are, currently, the most popular choice for any speech recognition system, though one of the shortcomings of MFCCs is that the signal is assumed to be stationary within the given time frame and is therefore unable to analyze non-stationary signal. To overcome this problem several researchers used different types of modulation/demodulation (AM-FM) techniques for extracting features from speech signal. In this paper, several techniques using the AM and FM model for a broadband signal such as speech and their use in feature extraction in speech recognition are outlined. Also, the use of Amplitude Modulation (AM), Frequency Modulation (FM), and modulation with Teager Energy Cepstral Coefficients (TECC) is studied.

© 2010 IUP. All Rights Reserved.

Design of Low Complexity Cosine Modulated Filter Bank Transmultiplexer for Unknown Channels

-- Manoj V J and Elizabeth Elias

The design of Low Complexity Cosine Modulated Filter Bank Transmultiplexer (LC CMFB TMUX) is given in this paper. CMFB TMUX is designed and the coefficients of the transmitting and receiving low-pass filters are synthesized in Canonic Signed Digit (CSD) format using Genetic Algorithm (GA). Chromosomes are encoded as ternary digit strings. Modified crossover and mutation techniques are used to preserve the canonical property of the Signed Power of Two (SPT) representations. Simulation results show that LC CMFB TMUX designed using the proposed algorithm has better Signal to Interference Ratio (SIR) and frequency responses than those of LC CMFB TMUX obtained by rounding the coefficients of low-pass filters.

© 2010 IUP. All Rights Reserved.

Design, Implementation and Performance Evaluation of Synchronous and Asynchronous Arbiters

-- Tamilarasi M, Shankar R,
Jaweth Akther, Thirumala Rao,
Manishekar C and Ramakrishnan N

Arbiters are electronic devices used in digital systems to order computational activities for shared resources. Asynchronous digital circuit designs claim to yield better results in the following areas of designers' interest: power efficiency, modularity, average-case performance, clock skew, adaptability to processing and environmental variations, concurrency, reusability, noise immunity and metastability. This paper presents the design and performance evaluation of a 4 ´ 1 asynchronous arbiter. In order to compare the performance of this asynchronous arbiter, a synchronous arbiter with similar specifications as that of asynchronous arbiter has been designed. The arbiters have been designed, coded and simulated using Verilog Hardware Description Language (HDL). The hex file has been generated using Xilinx tool and downloaded into the Field Programmable Gate Array (FPGA) kit. The measured performance parameters indicate that the asynchronous 4 ´ 1 arbiter consumes less power, offers higher throughput, higher frequency of operation and lower latency, compared to the synchronous 4 ´ 1 arbiter.

© 2010 IUP. All Rights Reserved.

Performance of a Variable Envelope Detector-Based Polar Transmitter for OFDM Systems

-- V K Dwivedi, S Tripathi,
V S Tripathi, R Tripathi and S Tiwari

Orthogonal Frequency Division Multiplexing (OFDM) is a modulation scheme suitable for high speed wireless links. In this paper, a new CMOS variable envelope detector-based polar transmitter for OFDM systems is designed, which is based on 90 nm CMOS technology. This 90 nm CMOS transmitter works in multilevel mode in such a way that it may switch up or switch down the transmitted voltage level according to Channel State Information (CSI). A digital envelope modulator, as a part of polar transmitter architecture for the 802.11 a/g WLAN OFDM standard is used. Assuming the knowledge of the instantaneous channel gain estimation for all users, the paper proposes an OFDM dynamic subcarrier allocation scheme to maintain optimum SNR level of the subchannels which are in deep fade. Simulation results show that system performance improves in terms of BER and SNR.

© 2010 IUP. All Rights Reserved.

Fractal Image Compression with Approximation Error-Based Suitable Domain Search

-- Vijayshri Chaurasia and Ajay Somkuwar

Image compression techniques are used to ensure the conservation of storage space and fast data transmission. Fractal image compression facilitates a very high compression ratio, fast decompression and resolution independence. This technique consumes a lot of time in its compression phase. This paper proposes an approximation error-based technique to reduce the amount, as well as complexity, of computations involved in suitable domain search, and the effect of image size variation on the performance of the scheme is also investigated.

© 2010 IUP. All Rights Reserved.

A High Speed Voltage Mode CMOS WTA Circuit for Image Processing

-- K L Baishnab, Amlan Nag and F A Talukdar

The design and simulation of a novel CMOS voltage mode Winner-Take-All (WTA) circuit are described in this paper. The circuit employs additional inhibitory and local excitatory feedback based on a common voltage computation, and this improves both the speed and precision drastically. As a result, a single stage cell provides better resolution and speed in comparison to previous works like Choi and Sheu (1993), where cascading was necessary to improve resolution, and Donckers et al. (1999). However, in an earlier work, Rahaman et al. (2009) observed that the resolution was 0.5 mV and the circuit was functioning for only two cells, and it also had a low dynamic range. Whereas the circuit described in this paper is tested with five contending cells and it shows better dynamic range as well as resolution. The simulations in Cadence show that a single cell can resolve voltage differences as small as 0.1 mV in about 60-80 ns, in comparison to the resolution of 100 mV in Choi and Sheu (1993) and 0.5 mV in Rahaman et al. (2009). Detailed simulation results along with appropriate mathematical relations have been presented. This circuit is a fundamental building block in the competitive layer of self-organizing neural networks, nonlinear filters, fuzzy and neuromorphic systems.

© 2010 IUP. All Rights Reserved.