The recent thrust towards high-speed, high-density and high-performance VLSI designs has presented several new challenges for today's circuit designers as well as CAD tool providers. At high speeds, previously neglected effects of interconnects are increasingly tending to impair the signals. This has warranted new measures to preserve the integrity of signal propagation in high-speed designs. This paper discusses the issues and the basic concepts associated with the emerging field of signal integrity. It also discusses various interconnect models to address signal integrity and its associated simulation challenges.

In the rapidly expanding world of micro-electronics, the increasingly faster and smaller circuit designs are leading to new and more complex effects in circuit signals, which are proving to be extremely problematic in the design and fabrication of high-speed circuits and systems. These effects, particularly those of the interconnects, were ignored in the past when the Rise-time of the clock signal was significantly less than the clock period; however, as the rise-times decreased and clock frequencies increased, the interconnects have come to be the limiting factor in circuit designs. These problems have been compounded by the factors such as the continuous demand for device size shrinking and low power consumption. In addition, the recent trend towards increased integration of mixed-domain blocks such as analog, digital, EM, optical and MEMS, etc., has further complicated the modeling/analysis/optimization of high-speed designs. The above factors have been acting as catalysts for the new emerging area of "Signal Integrity".

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